The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including high mobility semiconductor material fins having a faceted bottom surface which is present in a dielectric material and a method of forming the same.
The use of non-planar semiconductor devices such as, for example, silicon fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Silicon fin field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. In order to extend these devices for multiple technology nodes such as, for example, 10 nm and beyond, there is a need to boost the performance with high-mobility channels.
In such FinFET devices, fins containing a silicon germanium alloy or a III-V compound semiconductor are examples of promising channel materials because of their high-carrier mobility which enhances device performance at smaller device sizes. Formation of such high channel mobility fins is challenging due to the lattice mismatch of those semiconductor materials with silicon. Typically, silicon germanium alloy fins (or III-V compound semiconductor fins) are formed by epitaxially growing a layer of silicon germanium alloy or a III-V compound semiconductor on a bulk silicon substrate. The layer of silicon germanium alloy or III-V compound semiconductor is then patterned utilizing extreme ultraviolet (EUV) lithography. The use of EUV lithography is an expensive method to form high channel mobility fins having tight fin pitches.
Also, disconnecting high channel mobility fins from the bulk silicon substrate to create a fin-on-insulator structure has many device performance enhancing benefits such as, for example, lower leakage. Creating such structures via wafer bonding and fin cutting is very expensive and works only on the whole substrate, but not only in selected regions of the substrate.
As such, there is a need for providing high channel mobility fin-on-insulator structures which avoids the need to use EUV lithography to define the fins, and wafer bonding and fin cutting to disconnect the fins from the bulk substrate.